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opa564 www.ti.com sbos372e C october 2008 C revised january 2011 1.5a, 24v, 17mhz power operational amplifier check for samples: opa564 1 features description 23 ? high output current: 1.5a ? wide power-supply range: the opa564 is a low-cost, high-current operational amplifier that is ideal for driving up to 1.5a into C single supply: +7v to +24v reactive loads. the high slew rate provides 1.3mhz C dual supply: 3.5v to 12v full-power bandwidth and excellent linearity. these ? large output swing: 20v pp at 1.5a monolithic integrated circuits provide high reliability in demanding powerline communications and motor ? fully protected: control applications. C thermal shutdown the opa564 operates from a single supply of 7v to C adjustable current limit 24v, or dual power supplies of 3.5v to 12v. in ? diagnostic flags: single-supply operation, the input common-mode C over-current range extends to the negative supply. at maximum output current, a wide output swing provides a 20v pp C thermal shutdown (i out = 1.5a) capability with a nominal 24v supply. ? output enable/ shutdown control the opa564 is internally protected against ? high speed: over-temperature conditions and current overloads. it C gain-bandwidth product: 17mhz is designed to provide an accurate, user-selected C full-power bandwidth at 10v pp : current limit. two flag outputs are provided; one 1.3mhz indicates current limit and the second shows a thermal over-temperature condition. it also has an C slew rate: 40v/ m s enable/ shutdown pin that can be forced low to shut ? diode for junction temperature down the output, effectively disconnecting the load. monitoring the opa564 is housed in a thermally-enhanced, ? hsop-20 powerpad ? package surface-mount powerpad ? package (hsop-20) with (bottom- and top-side thermal pad versions) the choice of the thermal pad on either the top side or the bottom side of the package. operation for both applications versions is specified over the industrial temperature ? powerline communications range, C 40 c to +85 c. ? valve, actuator driver opa564 related products ? v com driver features device ? motor driver zer ? -drift pga with 2-channel input pga112 ? audio power amplifier mux and spi ? power-supply output amplifier zer ? -drift operational amplifier, opa365 50mhz, rri/o, single-supply ? test equipment amplifier quad operational amplifier, jfet ? transducer excitation tl074 input , low noise ? laser diode driver power operational amplifier, 1.2a, opa561 ? general-purpose linear power 15v, 17mhz, 50v/ m s booster 1 please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 powerpad is a trademark of texas instruments, inc. 3 all other trademarks are the property of their respective owners. production data information is current as of publication date. ? 2008 C 2011, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters.
opa564 sbos372e C october 2008 C revised january 2011 www.ti.com this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. package/ordering information (1) package product package-lead designator package marking hsop-20 (powerpad on bottom) dwp opa564 opa564 hsop-20 (powerpad on top) dwd opa564 (1) for the most current package and ordering information, see the package option addendum at the end of this document, or see the ti web site at www.ti.com . absolute maximum ratings (1) over operating free-air temperature range (unless otherwise noted). opa564 unit supply voltage, v s = (v+) C (v C ) +26 v voltage (2) (v C ) C 0.4 to (v+)+0.4 v signal input current through esd diodes (2) 10 ma terminals maximum differential voltage across inputs (3) 0.5 v voltage (v C ) C 0.4 to (v+)+0.4 v signal output terminals current (4) 10 ma output short-circuit (5) continuous operating junction temperature, t j C 40 to +125 c storage temperature, t a C 55 to +150 c junction temperature, t j +150 c human body model (hbm) 4000 v esd ratings charged device model (cdm) 1000 v machine model (mm) 200 v (1) stresses above these ratings may cause permanent damage. exposure to absolute maximum conditions for extended periods may degrade device reliability. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not supported. (2) input terminals are diode-clamped to the power-supply rails. signals that can swing more than 0.4v beyond the supply rails should be current limited to 10ma or less. (3) refer to figure 43 for information on input protection. see input protection section. (4) output terminals are diode-clamped to the power-supply rails. input signals forcing the output terminal more than 0.4v beyond the supply rails should be current limited to 10ma or less. (5) short-circuit to ground within soa. see power dissipation and safe operating area for more information. 2 submit documentation feedback ? 2008 C 2011, texas instruments incorporated product folder link(s): opa564
opa564 www.ti.com sbos372e C october 2008 C revised january 2011 electrical characteristics boldface limits apply over the specified temperature range: t a = C 40 c to +85 c. at t case = +25 c, v s = 12v, r load = 20k ? to gnd, r set = 7.5k , and e/ s pin enabled, unless otherwise noted. opa564 parameters conditions min typ max unit offset voltage input offset voltage v os v cm = 0v 2 20 mv vs temperature dv os /dt 10 m v/ c vs power supply psrr v cm = 0v, v s = 3.5v to 13v 10 150 m v/v input bias current input bias current (1) i b v cm = 0v 10 100 pa vs temperature see figure 10 , typical characteristics input offset current (1) i os 10 100 pa noise input voltage noise density e n f = 1khz 102.8 nv/ hz f = 10khz 20 nv/ hz f = 100khz 8 nv/ hz input current noise i n f = 1khz 4 fa/ hz input voltage range common-mode voltage range: v cm linear operation (v C ) (v+) C 3 v common-mode rejection ratio cmrr v cm = (v C ) to (v+) C 3v 70 80 db vs temperature see figure 9 , typical characteristics input impedance differential ? || pf 10 12 || 16 common-mode ? || pf 10 12 || 9 open-loop gain open-loop voltage gain a ol v out = 20v pp , r load = 1k ? 80 108 db v out = 20v pp , r load = 10 ? 93 db frequency response gain-bandwidth product (1) gbw r load = 5 ? 17 mhz slew rate sr g = 1, 10v step 40 v/ m s full power bandwidth g = +2, v out = 10v pp 1.3 mhz settling time 0.1% g = +1, 10v step, c load = 100pf 0.6 m s 0.01% g = +1, 10v step, c load = 100pf 0.8 m s total harmonic distortion + noise thd+n f = 1khz, r load = 5 ? , g = +1, v out = 5v p 0.003 % output voltage output: v out positive i out = 0.5a (v+) C 1 (v+) C 0.4 v negative i out = C 0.5a (v C )+1 (v C )+0.3 v positive i out = 1.5a (v+) C 2 (v+) C 1.5 v negative i out = C 1.5a (v C )+2 (v C )+1.1 v (1) see typical characteristics . ? 2008 C 2011, texas instruments incorporated submit documentation feedback 3 product folder link(s): opa564
opa564 sbos372e C october 2008 C revised january 2011 www.ti.com electrical characteristics (continued) boldface limits apply over the specified temperature range: t a = C 40 c to +85 c. at t case = +25 c, v s = 12v, r load = 20k ? to gnd, r set = 7.5k , and e/ s pin enabled, unless otherwise noted. opa564 parameters conditions min typ max unit output, continued maximum continuous current, dc i out 1.5 (2) a output impedance, closed loop r o f = 100khz 10 ? output impedance, open loop z o g = +2, f = 100khz see figure 24 , typical characteristics output current limit range (3) 0.4 to 2.0 a current limit equation i lim a (4) (5) solved for r set (current limit) r set ? (24k/i lim ) C 5k ? ? current limit accuracy i lim = 1.5a 10 % current limit overshoot (6) (7) v in = 5v pulse (200ns t r ), g = +2 50 % output shut down output impedance (8) 6 || 120 g ? || pf capacitive load drive c load see figure 6 , typical characteristics digital control enable/ shutdown mode input v dig = +3.3v to +5.5v referenced to v C v e/ s high (output enabled) e/ s pin open or forced high (v C )+2 (v C )+v dig v v e/ s low (output shut down) e/ s pin forced low (v C ) (v C )+0.8 v i e/ s high (output enabled) e/ s pin indicates high 10 m a i e/ s low (output shut down) e/ s pin indicates low 1 m a output shutdown time 1 m s output enable time 3 m s current limit flag output normal operation sinking 10 m a 0 (v C )+0.8 v current-limited sourcing 20 m a (v C )+2 v dig v thermal shutdown normal operation sinking 200 m a 0 (v C )+0.8 v thermally shutdown (9) sourcing 200 m a (v C )+2 v dig v +140 to junction temperature at shutdown (10) c +157 hysteresis (10) 15 to 19 c t sense diode ideality factor h 1.033 (2) under safe operating conditions. see power dissipation and safe operating area for safe operating area (soa) information. (3) minimum current limit is 0.4a. see adjustable current limit in the applications section. (4) quiescent current increases when the current limit is increased (see typical characteristics ). (5) r set (current limit) can range from 55k ? (i out = 400ma) to 10k ? (i out = 1.6a typ). see adjustable current limit in the applications section. (6) see typical characteristics . (7) transient load transition time must be 200ns. (8) see enable/shutdown (e/s) pin in the applications section. (9) when sourcing, the v dig supply must be able to supply the current. (10) characterized, but not production tested. 4 submit documentation feedback ? 2008 C 2011, texas instruments incorporated product folder link(s): opa564 i 20000 x lim @ 1.2v 5000 + r set
opa564 www.ti.com sbos372e C october 2008 C revised january 2011 electrical characteristics (continued) boldface limits apply over the specified temperature range: t a = C 40 c to +85 c. at t case = +25 c, v s = 12v, r load = 20k ? to gnd, r set = 7.5k , and e/ s pin enabled, unless otherwise noted. opa564 parameters conditions min typ max unit power supply (11) specified voltage range v s 12 v operating voltage range 7 24 v quiescent current (12) i q i out = 0 39 50 ma over temperature 50 ma quiescent current in shutdown mode i qsd 5 ma specified voltage for digital v dig (v C ) + 3.0 (v C ) + 5.5 v digital quiescent current i dig v dig = 5v 43 100 m a temperature range specified range C 40 +85 c operating range C 40 +125 (13) c thermal resistance hsop-20 dwp powerpad (pad down) q ja high k board 33 c/w q jc 50 c/w q jp 1.83 c/w q jb 22 c/w hsop-20 dwd powerpad (pad up) (14) q ja high k board 45.5 c/w q jc 6.3 c/w q jb 22 c/w (11) power-supply sequencing requirements must be observed. see power supplies section for more information. (12) quiescent current increases when the current limit is increased (see typical characteristics ). (13) the opa564 typically goes into thermal shutdown at a junction temperature above +140 c. (14) thermal modeling of the dwd-20 package was done based on a 1-inch aavid thermalloy heatsink (thermalloy part no. 65810). ? 2008 C 2011, texas instruments incorporated submit documentation feedback 5 product folder link(s): opa564
opa564 sbos372e C october 2008 C revised january 2011 www.ti.com pin configurations OPA564AIDWP opa564aidwd hsop-20 hsop-20 powerpad on bottom powerpad on top pin descriptions OPA564AIDWP opa564aidwd (pad down) (pad up) pin no. pin no. name description 1, 10, 11, 20 1, 10, 11, 20 v C C supply for amplifier, pwr out, and metal powerpad 2 19 v+ +supply for signal amplifier thermal over temperature flag; flag is high when alarmed and device has 3 18 t flag gone into thermal shutdown. 4 17 e/ s enable/ shutdown output stage; take e/ s low to shut down output 5 16 +in noninverting op amp input 6 15 C in inverting op amp input +supply for digital flag and e/ s (referenced to v C ). 7 14 v dig valid range is (v C ) + 3.0v v dig (v C ) + 5.5v. 8 13 i flag current limit flag; active high 9 12 i set current limit set (see applications section) 12 9 t sense temperature sense pin for use with tmp411 13, 14 7, 8 v C pwr C supply for power output stage 15, 16 5, 6 v out output voltage; r o is high impedance when shut down 17, 18, 19 3, 4, 2 v+ pwr +supply for power output stage 6 submit documentation feedback ? 2008 C 2011, texas instruments incorporated product folder link(s): opa564 12 3 4 5 6 7 8 9 10 2019 18 17 16 15 14 13 12 11 v - v+ pwrv+ pwr v+ pwr v out v out v pwr - v pwr - t sense v - v - v+ t flag e/ s +in- in v dig i flag i set v - powerpad heat sink (located on top side) (2) (2) powerpad is internally connected to v . - 12 3 4 5 6 7 8 9 10 2019 18 17 16 15 14 13 12 11 v - v+ t flag e/ s +in - in v dig i flag i set v - v - v+ pwrv+ pwr v+ pwr v out v out v pwr - v pwr - t sense v - powerpad heat sink (located on bottom side) (1) (1) powerpad is internally connected to v , soldering the powerpad to the pcb is always required, even with applications that have low power dissipation. -
opa564 www.ti.com sbos372e C october 2008 C revised january 2011 functional pin diagram ? 2008 C 2011, texas instruments incorporated submit documentation feedback 7 product folder link(s): opa564 enable/shutdown v - current limit flag thermal flag v dig v+ enable/shutdown current limit flag thermal flag v dig v+ - in +in OPA564AIDWP opa564aidwd current limit set r set t sense v out (2) (19) (17, 18) (6)(5) (1, 10, 11, 20) (13, 14) (7) (3) (8) (4) (12) (9) (15, 16) v - - in +in current limit set r set t sense v out (19) (2) (3, 4) (15)(16) (1, 10, 11, 20) (7, 8) (14) (18) (13) (17) (9) (12) (5, 6)
opa564 sbos372e C october 2008 C revised january 2011 www.ti.com typical characteristics at t case = +25 c, v s = 12v, r load = 20k ? to gnd, r set = 7.5k , and e/ s pin enabled, unless otherwise noted. quiescent current vs supply voltage output voltage swing vs output current figure 1. figure 2. large ? signal step response, no load large ? signal step response figure 3. figure 4. small ? signal step response small ? signal overshoot vs load capacitance figure 5. figure 6. 8 submit documentation feedback ? 2008 C 2011, texas instruments incorporated product folder link(s): opa564 time (250ns/div) 10mv/div r = c = 0pf load load no load g = 1 - v out v in 2v/div time (250ns/div) inputoutput unloaded g = +1 v = 9v in pp 1412 10 86 4 2 0 - 2 - 4 - 6 - 8 - 10 - 12 - 14 0 0.2 output current (a) output voltage (v) 1.6 0.4 0.6 0.8 1.0 1.2 1.4 v = 3.5v s v = 12v s +125 c +25 c - 40 c r = 7.5k set w 1ms current pulses v = 12v s 6050 40 30 20 10 0 overshoot (%) 10 100 1k 10k 100k capacitance (pf) v = 12v s g = +1 g = +10 g = 10 - g = 1 - 2v/div time (250ns/div) inputoutput 5 load g = +1 v = 9v w in pp 5048 46 44 42 40 38 36 34 32 30 quiescent current (ma) 6 10 20 24 supply voltage (v) 8 12 14 16 18 22 r = 7.5k set w r = 40k set w r = 100k set w
opa564 www.ti.com sbos372e C october 2008 C revised january 2011 typical characteristics (continued) at t case = +25 c, v s = 12v, r load = 20k ? to gnd, r set = 7.5k , and e/ s pin enabled, unless otherwise noted. i q vs temperature offset voltage vs temperature figure 7. figure 8. a ol , psrr, and cmrr vs temperature i b vs temperature figure 9. figure 10. i q , shutdown vs temperature i dig vs temperature figure 11. figure 12. ? 2008 C 2011, texas instruments incorporated submit documentation feedback 9 product folder link(s): opa564 100 8060 40 20 0 digital current ( a) m - 75 - 50 - 25 0 25 50 75 100 125 temperature ( c) 5045 40 35 30 25 20 quiescent current (ma) - 75 - 50 - 25 0 25 50 75 100 125 temperature ( c) r = 7.5k w set 2.01.5 1.0 0.5 0 quiescent current, shutdown (ma) - 75 - 50 - 25 0 25 50 75 100 125 temperature ( c) 2015 10 50 5 1015 20 - -- - offset voltage (mv) - 75 - 50 - 25 0 25 50 75 100 125 temperature ( c) 300250 200 150 100 50 0 50 100150 200 250 300 - -- - - - common-mode rejection ratio, power-supply rejection ratio, open-loop gain ( v/v) m - 75 - 50 - 25 0 25 50 75 100 125 temperature ( c) cmrr psrr a ol 22002000 1800 1600 1400 1200 1000 800600 400 200 0 200 - input bias current (pa) - 75 - 50 - 25 0 25 50 75 100 125 temperature ( c) i b+ i b - i os
opa564 sbos372e C october 2008 C revised january 2011 www.ti.com typical characteristics (continued) at t case = +25 c, v s = 12v, r load = 20k ? to gnd, r set = 7.5k , and e/ s pin enabled, unless otherwise noted. common-mode rejection ratio and gain and phase vs frequency power-supply rejection ratio vs frequency figure 13. figure 14. output voltage swing vs frequency output voltage swing vs frequency figure 15. figure 16. total harmonic distortion + noise vs amplitude total harmonic distortion + noise vs amplitude figure 17. figure 18. 10 submit documentation feedback ? 2008 C 2011, texas instruments incorporated product folder link(s): opa564 2520 15 10 50 output voltage (v ) pp 10k 100k 1m 10m 100m frequency (hz) 100 w 10 w v = 12v g = +1 s 0.01 0.1 1 10 100 1 0.1 0.01 0.001 0.0001 total harmonic distortion + noise (%) r = 10 load w r = 5 load w r = 60 load w r = no load load v amplitude (v ) out p v = 12v s f = 1khz g = 10 - 100 8060 40 20 0 cmrr, psrr (db) 10 100 10k 1k 100k frequency (hz) v = 12v s cmrr - psrr +psrr 120100 8060 40 20 0 frequency (hz) gain (db) 0- 45 - 90 - 135 - 180 phase ( ) 10k 100k 1m 10m 40m v = 12v r = 1k s load w gain phase 10 100 1k 0.01 0.1 1 10 100 1 0.1 0.01 0.001 0.0001 total harmonic distortion + noise (%) r = 10 load w r = 5 load w r = 60 load w r = no load load v amplitude (v ) out p v = 12v s f = 1khzg = +1 15.012.5 10.0 7.55.0 2.5 0 output voltage (v ) pp 10k 100k 1m 10m 100m frequency (hz) 10 w 100 w v = 12v g = +1 s
opa564 www.ti.com sbos372e C october 2008 C revised january 2011 typical characteristics (continued) at t case = +25 c, v s = 12v, r load = 20k ? to gnd, r set = 7.5k , and e/ s pin enabled, unless otherwise noted. total harmonic distortion + noise vs amplitude total harmonic distortion + noise vs frequency figure 19. figure 20. total harmonic distortion + noise vs frequency total harmonic distortion + noise vs frequency figure 21. figure 22. input voltage spectral noise and current noise vs frequency open-loop output impedance (no load) figure 23. figure 24. ? 2008 C 2011, texas instruments incorporated submit documentation feedback 11 product folder link(s): opa564 1k 100 10 1 1k100 10 1 voltage noise (nv/ ) hz ? current noise (fa/ ) hz ? 10 100 1k 10k 100k frequency (hz) v = 12v s voltage noise current noise 10 100 1k 10k 100k frequency (hz) 1 0.1 0.01 0.001 0.0001 total harmonic distortion + noise (%) g = +1 v = 5v out p r = load 10 w r = load 5 w r = load 60 w r = load no load 10 100 1k 10k 100k frequency (hz) 1 0.1 0.01 0.001 0.0001 total harmonic distortion + noise (%) g = 10 v = 8v - out p r = load 10 w r = load 5 w r = load 60 w r = load no load 10 100 1k 10k 100k frequency (hz) 1 0.1 0.01 0.001 0.0001 total harmonic distortion + noise (%) g = +10 v = 8v out p r = load 10 w r = load 5 w r = load 60 w r = load no load 0.01 0.1 1 10 100 v amplitude (v ) out p 1 0.1 0.01 0.001 0.0001 total harmonic distortion + noise (%) v = 12v s f = 1khzg = +10 r = 10 load w r = 5 load w r = 60 load w r = no load load 10k 1k 100 10 1 impedance ( ) w 1 10 100 1k 10k 100k 1m 10m 100m frequency (hz) i = 0a dc out
opa564 sbos372e C october 2008 C revised january 2011 www.ti.com typical characteristics (continued) at t case = +25 c, v s = 12v, r load = 20k ? to gnd, r set = 7.5k , and e/ s pin enabled, unless otherwise noted. input bias current vs closed-loop output impedance (no load) common-mode voltage figure 25. figure 26. enable response r load = 100 shutdown time (inverting configuration) figure 27. figure 28. enable time (inverting configuration) current limit percent error vs r set figure 29. figure 30. 12 submit documentation feedback ? 2008 C 2011, texas instruments incorporated product folder link(s): opa564 5040 30 20 10 0 10 - input bias current (pa) - 12 - 10 - 8 - 6 - 4 - 2 0 2 4 6 8 10 common-mode voltage (v ) cm r = 10k r = 100 v = 6v ww - f load out 2v/div time (1 s/div) m v out e/s v - 0v 2v/div time (100ns/div) r = 10k r = 100 v = 6v w w - f load out v out e/s v - 0v 10k 1k 100 10 1 0.1 0.01 impedance ( ) w 10 100 1k 10k 100k 1m 10m 100m frequency (hz) i = 0a dc gain = 1v/v out v out ch1: 0v ch2: 0v e/s time (500 s/div) m 1v/div r = 100 , g = +1 load w v = 1v in 6050 40 30 20 10 0 1020 30 40 -- - - current limit error (%) 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k r ( ) w set meanmean +3 mean 3 s - s
opa564 www.ti.com sbos372e C october 2008 C revised january 2011 typical characteristics (continued) at t case = +25 c, v s = 12v, r load = 20k ? to gnd, r set = 7.5k , and e/ s pin enabled, unless otherwise noted. output current limit vs r set output current limit vs r set (sourcing current) (sinking current) figure 31. figure 32. quiescent current increase vs r set offset voltage production distribution figure 33. figure 34. ? 2008 C 2011, texas instruments incorporated submit documentation feedback 13 product folder link(s): opa564 1.81.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 output current limit (a) 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k r ( ) w set mean mean 3 mean +3 calculated value - s s 54 3 2 1 0 i increase (ma) q 5k 15k 25k 45k 35k 55k 65k 75k r ( ) w set 1.81.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 output current limit (a) 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k r ( ) w set mean mean 3 mean +3 calculated value - s s population - 18.0 - 16.2 - 14.4 - 12.6 - 10.8 - 9.0 - 7.2 - 5.4 - 3.6 - 1.8 0 1.8 3.6 5.4 7.2 9.0 10.8 12.6 14.4 16.2 18.0 offset voltage (mv)
opa564 sbos372e C october 2008 C revised january 2011 www.ti.com application information sequencing of power supplies must assure that the basic configuration digital supply voltage (v dig ) be applied before the supply voltage to prevent damage to the opa564. figure 35 shows the opa564 connected as a basic figure 36 shows acceptable versus unacceptable noninverting amplifier. however, the opa564 can be power-supply sequencing. used in virtually any op amp configuration. power-supply terminals should be bypassed with low series impedance capacitors. the technique of using ceramic and tantalum capacitors in parallel is recommended. power-supply wiring should have low series impedance. (1) r set sets the current limit value from 0.4a to 1.5a. (2) e/ s pin forced low shuts down the output. (3) v dig must not exceed (v C ) + 5.5v; see figure 56 for examples of generating a signal for v dig . figure 35. basic noninverting amplifier power supplies the opa564 operates with excellent performance from single (+7v to +24v) or dual ( 3.5v to 12v) analog supplies and a digital supply of +3.3v to +5.5v (referenced to the v C pin). note that the analog power-supply voltages do not need to be symmetrical, as long as the total voltage remains below 24v. for example, the positive supply could be set to 14v with the negative supply at C 10v. most behaviors remain constant across the operating (1) the power-supply sequence illustrated in (a) is not allowed. voltage range. parameters that vary significantly with this power-supply sequence causes damage to the device. operating voltage are shown in the typical characteristics . figure 36. power-supply sequencing 14 submit documentation feedback ? 2008 C 2011, texas instruments incorporated product folder link(s): opa564 e/s (2) r set (1) 47 f m 0.1 f m v o v in v - i set opa564 47 f m 0.1 f m v dig (3) v+ voltage (v) time (s) voltage (v) time (s) voltage (v) time (s) (a) sequence not allowed (1) (b) sequence allowed (c) sequence allowed v supply v supply v supply v digital v digital v digital see note 1
opa564 www.ti.com sbos372e C october 2008 C revised january 2011 setting the current limit adjustable current limit leaving the i set pin unconnected damages the the opa564 provides over-current protection to the device. connecting i set directly to v C is not load through its accurate, user-adjustable current limit recommended because it programs the current limit (i set pin). the current limit value, i lim , can be set from far beyond the 1.5a capability of the device and 0.4a to 1.5a by controlling the current through the causes excess power dissipation. the minimum i set pin. setting the current limit does not require recommended value for r set is 7.5k ? , which special power resistors. the output current does not programs the maximum current limit to approximately flow through the i set pin. 1.9a. the maximum value for r set is 55k ? , which a simple resistor to the negative rail is sufficient for a programs the minimum current limit to approximately general, coarse limit of the output current. figure 30 0.4a. the simplest method for adjusting the current exhibits the percent of error in the transfer function limit (i lim ) uses a resistor or potentiometer connected between i set and i out versus the current limit set between the i set pin and v C , according to equation 1 . resistor, r set ; figure 31 and figure 32 show how this if i lim has been defined, r set can be solved by error translates to variation in i out versus r set . the rearranging equation 1 into equation 3 : dotted line represents the ideal output current setting which is determined by the following equation: (3) (1) r set in combination with a 5k ? internal resistor determines the magnitude of a small current that sets the mismatch errors between the current limit set the desired output current limit. mirror and the output stage are primarily a result of variations in the ~1.2v bandgap reference, an internal figure 37 shows a simplified schematic of the 5k resistor, the mismatch between the current limit opa564 current limit architecture. and the output stage mirror, and the tolerance and temperature coefficient of the r set resistor referenced to the negative rail. additionally, an increase in junction temperature can induce added mismatch in accuracy between the i set and i out mirror. see figure 53 for a method that can be used to dynamically change the current limit setting using a simple, zero drift current source. this approach simplifies the current limit equation to the following: (2) the current into the i set pin is determined by the npn current source. therefore, the errors contributed by the internal 1.2v bandgap reference and the 5k resistor mismatch are eliminated, thus improving the overall accuracy of the transfer function. in this case, the primary source of error in i set is the r set resistor tolerance and the beta of the npn transistor. it is important to note that the primary intent of the current limit on the opa564 is coarse protection of (1) at power-on, this capacitor is not charged. therefore, the the output stage; therefore, the user should exercise opa564 is programmed for maximum output current. capacitor caution when attempting to control the output current values > 1nf are not recommended. by dynamically toggling the current limit setting. figure 37. adjustable current limit predictable performance is better achieved by controlling the output voltage through the feedback loop of the opa564. ? 2008 C 2011, texas instruments incorporated submit documentation feedback 15 product folder link(s): opa564 r set @ 24k i w lim - 5k w r set opa564 5k w i lim @ 1.2v r + 5k w cl ( ) 20k v - i set 1.2v bandgap i i out lim 1nf(optional, for noisy environments) (1) i 20000 x lim @ 1.2v 5000 + r set i 20,000 lim i set @
opa564 sbos372e C october 2008 C revised january 2011 www.ti.com enable/ shutdown (e/ s) pin logic signal and the opa564 shutdown pin are referenced to the same potential. in this configuration, the output of the opa564 shuts down when the e/ s the logic pin and the opa564 enable can simply be pin is forced low. for normal operation (output connected together. shutdown occurs for voltage enabled), the e/ s pin must be pulled high (at least 2v levels of less than 0.8v. the opa564 is enabled at above v C ). to enable the opa564 permanently, the logic levels greater than 2v. in dual-supply operation, e/ s pin can be left unconnected. the e/ s pin has an the logic pin remains referenced to a logic ground. internal 100k ? pull-up resistor. when the output is however, the shutdown pin of the opa564 continues shut down, the output impedance of the opa564 is to be referenced to v C . 6g || 120pf. the output shutdown output voltage versus output current is shown in figure 42 . although thus, in a dual-supply system, to shut down the the output is high-impedance when shut down, there opa564 the voltage level of the logic signal must be is still a path through the feedback network into the level-shifted by some means. one way to shift the input stage to ground; see figure 43 . to prevent logic signal voltage level is by using an optocoupler, damage to the opa564, ensure that the voltage as figure 38 shows. across the input terminals +in and C in does not exceed 0.5v, and that the current flowing through the input terminals does not exceed 10ma when operated beyond the supply rails, v C and v+. refer to the input protection section. input protection electrostatic discharge (esd) protection followed by back-to-back diodes and input resistors (see figure 43 ) are used for input protection on the opa564. exceeding the turn-on threshold of these diodes, as in a pulse condition, can cause current to flow through the input protection diodes because of the finite slew rate of the amplifier. if the input current is not limited, the back-to-back diodes and the input devices can be destroyed. sources of high input current can also cause subtle damage to the amplifier. although the unit may still be functional, (1) optional; may be required to limit leakage current of important parameters such as input offset voltage, optocoupler at high temperatures. drift, and noise may shift. figure 38. shutdown configuration for dual when using the opa564 as a unity-gain buffer supplies (using optocoupler) (follower), as an inverting amplifier, or in shutdown mode, the input voltage between the input terminals (+in and C in) must be limited so that the voltage to shut down the output, the e/ s pin is pulled low, no does not exceed 0.5v. this condition must be greater than 0.8v above v C . this function can be maintained across the entire common-mode range used to conserve power during idle periods. to return from v C to v+. if the inputs are taken above either the output to an enabled state, the e/ s pin should be supply rail, the current must be limited to 10ma pulled to at least 2.0v above v C . figure 27 shows the through the esd protection diodes. during excursions typical enable and shutdown response times. it past the rails, it is still necessary to limit the voltage should be noted that the e/ s pin does not affect the across the input terminals. if necessary, external internal thermal shutdown. back-to-back diodes should be added between +in when the opa564 will be used in applications where and C in to maintain the 0.5v requirement between the device shuts down, special care should be taken these connections. with respect to input protection. consider the following two examples. output shutdown the shutdown pin (e/ s) is referenced to the negative supply (v C ). therefore, shutdown operation is slightly different in single-supply and dual-supply applications. in single-supply operation, v C typically equals common ground. therefore, the shutdown 16 submit documentation feedback ? 2008 C 2011, texas instruments incorporated product folder link(s): opa564 optocoupler 4n38 e/s v+ (a) +5v (b) hct or ttl in hct or ttl in (a) (b) opa564 (1) v -
opa564 www.ti.com sbos372e C october 2008 C revised january 2011 figure 39 shows the amplifier in a follower when the device shuts down in this situation, the load configuration. the load is connected midway between pulls v out to ground. little or no current then flows the supplies, v+ and v C . through the input of the opa564. figure 39. shutdown equivalent circuit with load connected midway between supplies ? 2008 C 2011, texas instruments incorporated submit documentation feedback 17 product folder link(s): opa564 1.6k w 1.6k w 100 w 6g w 120pf v+ v+ v+v+ v - v - v - v - v out i 1 i 2 +in - in
opa564 sbos372e C october 2008 C revised january 2011 www.ti.com now consider figure 40 . here, the load is connected this current flow produces a voltage across the to v C . when the device shuts down, current flows inputs which is much greater than 0.5v, which from the positive input +in through the first 1.6k damages the opa564. a similar problem would occur resistor through an input protection diode, then if the load is connected to the positive supply. through the second 1.6k resistor, and finally through the 100 resistor to v C . caution this configuration damages the device. figure 40. shutdown equivalent circuit with load connected to v C : voltage across inputs during disable exceeds input requirements 18 submit documentation feedback ? 2008 C 2011, texas instruments incorporated product folder link(s): opa564 1.6k w 1.6k w 100 w 6g w 120pf v+ v+ v+v+ v - v - v - v - v out i 1 i 2 +in - in
opa564 www.ti.com sbos372e C october 2008 C revised january 2011 the solution is to place external protection diodes across the opa564 input. figure 41 illustrates this configuration. note this configuration protects the input during shutdown. figure 41. shutdown equivalent circuit with load connected to v C : protected input configuration ? 2008 C 2011, texas instruments incorporated submit documentation feedback 19 product folder link(s): opa564 1.6k w 1.6k w 100 w 6g w 120pf v+ v+ v+v+ v - v - v - v - v out i 1 i 2 +in - in external protection diodesrequired; use skyworks solutions inc. # sms3922-004lf or equivalent
opa564 sbos372e C october 2008 C revised january 2011 www.ti.com ensuring microcontroller compatibility within the optocoupler. a high logic level causes the opa564 to be enabled, and a low logic level shuts not all microcontrollers output the same logic state the opa564 down. in the configuration of after power-up or reset. 8051-type microcontrollers, figure 38 (b) , with the logic signal applied on the for example, output logic high levels while other anode side, a high level causes the opa564 to shut models power up with logic low levels after reset. in down, and a low level enables the op amp. the configuration of figure 38 (a) , the shutdown signal is applied on the cathode side of the photodiode figure 42. output shutdown output impedance figure 43. opa564: output shutdown equivalent circuit (with external feedback) 20 submit documentation feedback ? 2008 C 2011, texas instruments incorporated product folder link(s): opa564 500450 400 350 300 250 200 150 100 50 0 output current (pa) - 10 - 8 - 6 - 4 - 2 0 2 4 6 8 10 output voltage (v) v = 12v s output shutdown output voltage vs output current opa564 e/ = low (output shutdown) s v out i out test circuit r f 1.6k w 1.6k w 6g w r 1 120pf v+ v+ v+v+ v - v - v - v - v out external protectiondiodes as needed i 1 i 2 +in - in
opa564 www.ti.com sbos372e C october 2008 C revised january 2011 current limit flag depending on load and signal conditions, the thermal protection circuit may cycle on and off. this cycling the opa564 features a current limit flag (i flag ) that limits the amplifier dissipation, but may have can be monitored to determine if the load current is undesirable effects on the load. any tendency to operating within or exceeding the current limit set by activate the thermal protection circuit indicates the user. the output signal of i flag is compatible with excessive power dissipation or an inadequate standard cmos logic and is referenced to the heatsink. for reliable, long-term, continuous negative supply pin (v C ). a voltage level of + 0.8v or operation, with i out at the maximum output of 1.5a, less with respect to v C indicates that the amplifier is the junction temperature should be limited to +85 c operating within the limits set by the user. a voltage maximum. figure 44 shows the maximum output level of +2.0v or greater with respect to v C indicates current versus junction temperature for dc and rms that the opa564 is operating above (exceeds) the signal outputs. to estimate the margin of safety in a current limit set by the user. see setting the current complete design (including heatsink), increase the limit for proper current limit operation. ambient temperature until the thermal protection triggers. use worst-case loading and signal output stage compensation conditions. for good, long-term reliability, thermal protection should trigger more than 35 c above the the complex load impedances common in power op maximum expected ambient condition of the amp applications can cause output stage instability. application. for normal operation, output compensation circuitry is typically not required. however, if the opa564 is the internal protection circuitry of the opa564 was intended to be driven into current limit, an r/c designed to protect against overload conditions; it network (snubber) may be required. a snubber circuit was not intended to replace proper heatsinking. such as the one shown in figure 54 may also continuously running the opa564 into thermal enhance stability when driving large capacitive loads shutdown degrades reliability. (greater than 1000pf) or inductive loads (for example, motors or loads separated from the amplifier by long cables). typically, 3 ? to 10 ? in series with 0.01 m f to 0.1 m f is adequate. some variations in circuit value may be required with certain loads. output protection the output structure of the opa564 includes esd diodes (see figure 43 ). voltage at the opa564 output must not be allowed to go more than 0.4v beyond either supply rail to avoid damaging the device. reactive and electromagnetic field (emf)-generation loads can return load current to the amplifier, causing the output voltage to exceed the power-supply voltage. this damaging condition can be avoided with clamping diodes from the output terminal to the power supplies, as figure 54 and figure 44. maximum output current vs junction figure 55 illustrate. schottky rectifier diodes with a 3a temperature or greater continuous rating are recommended. thermal protection using t sense for measuring junction the opa564 has thermal sensing circuitry that helps temperature protect the amplifier from exceeding temperature the opa564 includes an internal diode for junction limits. power dissipated in the opa564 causes the temperature monitoring. the h -factor of this diode is junction temperature to rise. internal thermal 1.033. measuring the opa564 junction temperature shutdown circuitry disables the output when the die can be accomplished by connecting the t sense pin to temperature reaches the thermal shutdown a remote-junction temperature sensor, such as the temperature limit. the opa564 output remains shut tmp411 (see figure 57 ). down until the die has cooled sufficiently; see the electrical characteristics , thermal shutdown section. ? 2008 C 2011, texas instruments incorporated submit documentation feedback 21 product folder link(s): opa564 1.61.4 1.2 1.0 0.8 0.6 0.4 0.2 0 max i (a) out - 50 - 25 0 25 50 75 100 125 t ( c) j max i (dc) max i (rms) out out maximum output current vs junction temperature
opa564 sbos372e C october 2008 C revised january 2011 www.ti.com power dissipation and safe once the heatsink area has been selected, operating area worst-case load conditions should be tested to ensure proper thermal protection. power dissipation depends on power supply, signal, and load conditions. for dc signals, power dissipation space is equal to the product of output current (i out ) and the voltage across the conducting output transistor [(v+) C v out when sourcing; v out C (v C ) when sinking]. dissipation with ac signals is lower. application bulletin ab-039, power amplifier stress and power handling limitations ( sboa022 , available for download from www.ti.com ) explains how to calculate or measure power dissipation with unusual signals and loads. figure 45 shows the safe operating area at room temperature with various heatsinking efforts. note that the safe output current decreases as (v+) C v out or v out C (v C ) increases. figure 46 shows the safe operating area at various temperatures with the powerpad being soldered to a 2oz copper pad. the power that can be safely dissipated in the package is related to the ambient temperature and figure 45. safe operating area at room the heatsink design. the powerpad package was temperature specifically designed to provide excellent power dissipation, but board layout greatly influences the heat dissipation of the package. refer to the thermally-enhanced powerpad package section for further details. the relationship between thermal resistance and power dissipation can be expressed as: t j = t a + t ja t ja = p d q ja combining these equations produces: t j = t a + p d q ja where: t j = junction temperature ( c) t a = ambient temperature ( c) q ja = junction-to-ambient thermal resistance ( c/w) powerpad soldered to a 2oz copper pad. p d = power dissipation (w) figure 46. safe operating area at various ambient temperatures to determine the required heatsink area, required power dissipation should be calculated and the relationship between power dissipation and thermal resistance should be considered to minimize shutdown conditions and allow for proper long-term operation (junction temperature of +85 c or less). 22 submit documentation feedback ? 2008 C 2011, texas instruments incorporated product folder link(s): opa564 10.0 1.00.1 0.01 output current (a) 0 2 4 6 8 10 12 14 16 18 20 22 24 26 safe operating area at various ambient temperatures (powerpad soldered) t = 40 c - a t = 0 c t = +25 c t = +85 c t = +125 c a aa a (v+) v , (v ) (v) - out v out - - 10.0 1.00.1 output current (a) 0 2 4 6 8 10 12 14 16 18 20 22 24 26 (v+) v , (v ) (v) - out v out - - safe operating area at room temperature copper, soldered without forced air copper, soldered with 200lfm airflow
opa564 www.ti.com sbos372e C october 2008 C revised january 2011 for applications with limited board size, refer to thermally-enhanced powerpad figure 47 for the approximate thermal resistance package relative to heatsink area. increasing heatsink area the opa564 uses the hsop-20 powerpad dwp beyond 2in 2 provides little improvement in thermal and dwd packages, which are thermally-enhanced, resistance. to achieve the 33 c/w shown in the standard size ic packages. these packages enhance electrical characteristics , a 2oz copper plane size of power dissipation capability significantly and can be 9in 2 was used. the powerpad package is well-suited easily mounted using standard printed circuit board for continuous power levels from 2w to 4w, (pcb) assembly techniques, and can be removed depending on ambient temperature and heatsink and replaced using standard repair procedures. area. the addition of airflow also influences maximum power dissipation, as figure 48 illustrates. higher the dwp powerpad package is designed so that power levels may be achieved in applications with a the leadframe die pad (or thermal pad) is exposed on low on/off duty cycle, such as remote meter reading. the bottom of the ic, as shown in figure 49 a ; the dwd powerpad package has the exposed pad on the top side of the package, as shown in figure 49 b . the thermal pad provides an extremely low thermal resistance ( q jc ) path between the die and the exterior of the package. powerpad packages with exposed pad down are designed to be soldered directly to the pcb, using the pcb as a heatsink. texas instruments does not recommend the use of the of a powerpad package without soldering it to the pcb because of the risk of lower thermal performance and mechanical integrity. in addition, through the use of thermal vias, the bottom-side thermal pad can be directly connected to a power plane or special heatsink structure designed into the pcb. the powerpad should be at the same voltage potential as v C . soldering the bottom-side powerpad to the pcb is always required, even with applications that have low power dissipation. it figure 47. thermal resistance vs circuit board provides the necessary thermal and mechanical copper area connection between the leadframe die and the pcb. pad-up powerpad packages should have appropriately designed heatsinks attached. because of the variation and flexible nature of this type of heat sink, additional details should come from the specific manufacturer of the heatsink. figure 48. maximum power dissipation vs temperature ? 2008 C 2011, texas instruments incorporated submit documentation feedback 23 product folder link(s): opa564 65 4 3 2 1 0 power dissipation in package (w) 0 25 50 75 100 125 temperature ( c) no copper copper, soldered without forced air copper, soldered with 200lfm airflow maximum power dissipation vs temperature 4540 35 30 25 20 thermal resistance, ( c/w) ja 0 1 q 2 3 4 5 copper area (inches ) 2 opa564 surface mount package 2oz copper thermal resistance vs circuit board copper area
opa564 sbos372e C october 2008 C revised january 2011 www.ti.com figure 49. cross-section views holes under the powerpad package should be bottom-side powerpad assembly process connected to the internal plane with a complete 1. the powerpad must be connected to the most connection around the entire circumference of the negative supply of the device, v C . plated through-hole. 2. prepare the pcb with a top side etch pattern, as 7. the top-side solder mask should leave exposed shown in the attached thermal land pattern the terminals of the package and the thermal pad mechanical drawing. there should be etch for the area. the thermal pad area should leave the leads as well as etch for the thermal land. 13mil holes exposed. the larger 25mil holes outside the thermal pad area should be covered 3. place the recommended number of holes (or with solder mask. thermal vias) in the area of the thermal pad, as seen in the attached thermal land pattern 8. apply solder paste to the exposed thermal pad mechanical drawing. these holes should be area and all of the package terminals. 13mils (.013in, or 330.2 m m) in diameter. they are 9. with these preparatory steps completed, the kept small so that solder wicking through the powerpad ic is simply placed in position and run holes is not a problem during reflow. through the solder reflow operation as any 4. it is recommended, but not required, to place a standard surface-mount component. this small number of the holes under the package and processing results in a part that is properly outside the thermal pad area. these holes installed. provide an additional heat path between the for detailed information on the powerpad package copper land and ground plane and are 25mils including thermal modeling considerations and repair (.025in, or 635 m m) in diameter. they may be procedures, see technical brief slma002 , larger because they are not in the area to be powerpad thermally enhanced package , available soldered, so wicking is not a problem. this at www.ti.com . configuration is illustrated in the attached thermal land pattern mechanical drawing. 5. connect all holes, including those within the thermal pad area and outside the pad area, to the internal plane that is at the same voltage potential as v C . 6. when connecting these holes to the internal plane, do not use the typical web or spoke via connection methodology (as figure 50 shows). web connections have a high thermal resistance connection that is useful for slowing the heat transfer during soldering operations. this configuration makes the soldering of vias that have plane connections easier. however, in this figure 50. via connection methods application, low thermal resistance is desired for the most efficient heat transfer. therefore, the 24 submit documentation feedback ? 2008 C 2011, texas instruments incorporated product folder link(s): opa564 mold compound (epoxy) leadframe die pad exposed at base of the package leadframe (copper alloy) (a) dwp powerpad cross-section view (b) dwd powerpad cross-section view ic (silicon) die attach (epoxy) board external heatspreader power transistor chip die attach thermal paste die pad web or spoke via solid via not recommended recommended
opa564 www.ti.com sbos372e C october 2008 C revised january 2011 applications circuits the high output current and low supply of the opa564 make it a good candidate for driving laser diodes and thermoelectric coolers. figure 51 shows an improved howland current pump circuit. powerline communication powerline communication (plc) applications require some form of signal transmission over an existing ac power line. a common technique used to couple these modulated signals to the line is through a signal transformer. a power amplifier is often needed to provide adequate levels of current and voltage to drive the varying loads that exist on today s powerlines. one such application is shown in figure 52 . the opa564 is used to drive signals used in frequency modulation schemes such as fsk (frequency-shift keying) or ofdm (orthogonal frequency-division multiplexing) to transmit digital information over the powerline. the power output capabilities of the opa564 are needed to drive the current requirements of the transformer that is shown in the figure, coupled to the ac power line via a coupling capacitor. circuit protection is often needed or required to prevent excessive line voltages or (1) see figure 35 for an example of a basic noninverting amplifier with v dig not exceeding 5.5v. current surges from damaging the active circuitry in the power amplifier and application circuitry. figure 51. improved howland current pump (1) s 1 , s 2 , s 3 , and s 4 are schottky diodes. s 1 and s 2 are b350 or equivalent. s 3 and s 4 are bav99t or equivalent. (2) l 1 should be small enough so that it does not interfere with the bandwidth of interest but large enough to suppress transients that could damage the opa564. (3) d 1 is a transient suppression diode. for 24v supplies, use smbj12ca. for 12v supplies, use smbj6.0ca. voltage rating of transient voltage suppressor should be half the supply rating or less. (4) the minimum recommended value for r 4 is 7.5k . figure 52. powerline communication line coupling ? 2008 C 2011, texas instruments incorporated submit documentation feedback 25 product folder link(s): opa564 opa564 i set 47 m f r 2 1k w r 1 20k w r 4 1k w r 4 20k w r 5 50m w v o - 5v +1v/+1a v dig +5v 0.1 f m 0.1 f m 47 f m r set r 3 opa564 c 5 + c 6 r 1 c 1 c10pf 4 r f c f c 47 f m 3 c 0.1 f m 2 3 4 6 1 t 1 d 1 (3) smbj12ca or smbj6.0ca v s v dig input 1/2 v s e/s gnd s 2 (1) r 4 (4) s 1 (1) s 3 (1) s 4 (1) l 1 (2)
opa564 sbos372e C october 2008 C revised january 2011 www.ti.com programmable power supply for more information on this circuit, see the application bulletin dc motor speed controller: figure 53 shows the opa333 used to control i set in control a dc motor without tachometer feedback order to adjust the current limit of the opa564. ( sboa043 ), available for download at the ti web site. figure 54 shows a basic motor speed driver but does figure 56 shows two examples of generating the not include any control over the motor speed. for signal for v dig . figure 56 a uses an 1n4732a zener to applications where good control of the speed of the bias the v dig to precisely 4.7v above v C . figure 56 b motor is desired, but the precision of a tachometer uses a high-voltage subregulator to derive the v dig control is not required, the circuit in figure 55 voltage. figure 58 illustrates a detailed powerline provides control by using feedback of the current communication circuit. consumption to adjust the motor drive. figure 53. programmable current limit option (1) z 1 , z 2 = zener diodes (in5246 or equivalent). select z 1 and z 2 diodes that are capable of the maximum anticipated surge current. (2) s 1 , s 2 = schottky diodes (stps1l40 or equivalent). (3) c 1 = high-frequency bypass capacitors; c 2 = low-frequency bypass capacitors (minimum of 10 m f for every 1a peak current) figure 54. motor drive circuit 26 submit documentation feedback ? 2008 C 2011, texas instruments incorporated product folder link(s): opa564 g = - = - 4 r 2 r 1 v in v+ v dig v - r 1 5k w r 2 20k w opa564 10 w (non-inductive) motor 0.01 f m z 1 (1) z 2 s 2 s 1 (1) (2)(2) c 0.1 f 1 m c 0.1 f 1 m c 47 f 2 m c 47 f 2 m note (3) note (3) r 1 r f t1 2n2923 + +5v v+ v - i set i set i out v out v in v set r load opa564 opa333 r 5k set w c 100pf 1 v 100mv set v (1 + ) in r r f 1 r load i = out i lim i i lim set 20,000 @ i set @ i 20,000 lim i set (0.4a to 1.5a) = 20 a to 75 a m m v set (0.4a to 1.5a) = 100mv to 375mv and
opa564 www.ti.com sbos372e C october 2008 C revised january 2011 (1) i flag and t flag connections are not shown. (2) z 1 , z 2 = zener diodes (in5246 or equivalent). select z 1 and z 2 diodes that are capable of the maximum anticipated surge current. (3) s 1 , s 2 = schottky diodes (stps1l40 or equivalent). (4) c 1 = high-frequency bypass capacitors; c 2 = low-frequency bypass capacitors (minimum of 10 m f for every 1a peak current). figure 55. dc motor speed controller (without tachometer) figure 56. circuits for generating v dig ? 2008 C 2011, texas instruments incorporated submit documentation feedback 27 product folder link(s): opa564 +12v - 12v r m r = 12 w m dcmotor r 2 10k w r 1 1k w r set v in emf r s 1 w opa564 v dig (1) c 0.1 f 1 m c 0.1 f 1 m c 47 f 2 m c 47 f 2 m r 5k 3 w z 2 s 2 z 1 s 1 (2) (2) (3)(3) note (4) note (4) v+ v - v dig 10k w 4.7vzener 1n4732a (a) (b) 2 5 1 4 3 in c 1000 f m i1 c100nf i2 c 22 f m out i in i ro v rd v out i out r ext 5k w v in i d,c i d,d i gnd v d c d 47nf delay gnd reset out tle4275-q1
opa564 sbos372e C october 2008 C revised january 2011 www.ti.com figure 57. temperature measurement using t sense and tmp411 figure 58. detailed powerline communication circuit 28 submit documentation feedback ? 2008 C 2011, texas instruments incorporated product folder link(s): opa564 t sense 50 w v - 50pf d - d+ scl sda alert therm2 / therm gnd v+ +5v 0.1 f m 10k(typ) w 10k(typ) w 10k(typ) w 10k(typ) w smbus controller over-temperature fault opa564 tmp411 1 8 76 4 5 3 2 - in v+ v dig +in v out 4 3 1 5 2 u5 opa 365 avdd 1 ch1 2 ch0/vcal 3 vref 4 vout 5 gnd 6 sclk 7 dio 8 not cs 9 dvdd 10 u10 pga112 v- 1 v+ 2 tflg 3 e/s 4 +in 5 -in 6 vdig 7 iflag 8 iset 9 v- 10 v- 11 tsense 12 v-pwr 13 v-pwr 14 vout 15 vout 16 v+pwr 17 v+pwr 18 v+pwrsence 19 v- 20 gnd 21 gnd 22 gnd 23 gnd 24 gnd 25 gnd 26 gnd 27 gnd 28 gnd 29 gnd 30 gnd 31 gnd 32 gnd 33 gnd 34 gnd 35 power pad opa564 u4 OPA564AIDWP 1 2 3 4 5 6 7 8 9 10 11 12 j2 12 header 1 2 3 4 5 6 7 8 9 10 11 12 j3 12 header r8 30k r11 30k r13 6.8k r6 15k r10 3.3k r14 1.47k r7 2.67k c1 150pf c11 100nf c7 820pf c5 82pf c8 10nf c9 1.0uf c2 0.1uf r16 10.0k r19 2.49k r18 12.0k r23 10.0k r22 10.0k r21 1.0 ohms c13 0.1uf c16 0.1uf c17 0.1uf c19 10uf c18 0.1uf c20 0.1uf r17 16.5k r20 0 ohm r25 10k r24 10k c14 10 uf l1 1uh, 1.075a lb3218t1rom d5 b350a-13-f or equivalent d4 b350a-13-f test point 1 tp1 test point test point 1 tp8 test point test point 1 tp2 test point test point 1 tp3 test point test point 1 tp4 test point 1 2 jp5 jumper r31 3.83k r34 3.83k r28 15.4k r32 4.4k r35 4.4k r29 4.4k r41 0.0 ohm c23 470pf c29 82pf c24 1500pf c30 82pf c26 0.1uf c36 0.1uf c37 0.1uf d6 b350a-13-f d7 b350a-13-f gnd gnd d2 led d3 led d1 led r4 228 ohm r3 228 ohm r5 228 ohm gnd c12 2700pf c15 100nf gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd pwm2_gpio02 pwm1_gpio00 adcin adcin gnd +15v spistea_gpio19 spiclka_gpio18 txrx txdrven_gpio32 led gpio20 led gpio21 led gpio22 r26 150 ohm c21 33nf l2 330uh r27 150 ohm c22 22nf l3 470uh gnd txrx c40 10uf spisimoa_gpio16 spisomia_gpio17 r45 0 ohm r47 10k r46 10k r48 10k r49 10k spistea_gpio19 spiclka_gpio18 txdrven_gpio32 spisimoa_gpio16 spisomia_gpio17 test point 1 tp6 test point test point 1 tp7 test point test point 1 tp5 test point +3.3v +3.3v +3.3v +3.3v +3.3v +3.3v +3.3v +3.3v +3.3v +3.3v +15v +15v gnd test point 1 gnd test point r50 10k 4 3 1 5 2 u2 opa 365 c6 0.1uf gnd gnd +3.3v 4 3 1 5 2 u1 opa 365 4 3 1 5 2 u6 opa 365 4 3 1 5 2 u7 opa 365 c25 0.1uf gnd gnd +3.3v pad 1 p1 free pad pad 1 p2 free pad gnd heat sink pads c99 50pf 1smb5930 or equivalent gnd
opa564 www.ti.com sbos372e C october 2008 C revised january 2011 revision history note: page numbers for previous revisions may differ from page numbers in the current version. changes from revision d (november, 2010) to revision e page ? changed r cl to r set throughout document ......................................................................................................................... 1 ? updated absolute maximum ratings table, signal input terminals specifications; added new footnote .............................. 2 ? deleted current through back-to-back input protection diodes specification; added maximum differential voltage across inputs specification .................................................................................................................................................... 2 ? changed footnote (4) in absolute maximum ratings table .................................................................................................. 2 ? revised conditions for electrical characteristics table ......................................................................................................... 3 ? revised conditions for electrical characteristics table ......................................................................................................... 4 ? updated current limit equation .............................................................................................................................................. 4 ? changed ideality factor value for t sense parameter ............................................................................................................. 4 ? changed footnote (5) in electrical characteristics table ....................................................................................................... 4 ? revised conditions for electrical characteristics table ......................................................................................................... 5 ? deleted condition statement for i q and i qsd parameters in electrical characteristics table ................................................. 5 ? updated minimum value for v dig parameter in electrical characteristics table ................................................................... 5 ? changed description of v dig pin operation ........................................................................................................................... 6 ? updated condition statement for typical characteristics ..................................................................................................... 8 ? corrected y-axis values in figure 1 ...................................................................................................................................... 8 ? revised setting the current limit section to update maximum value for r set .................................................................. 15 ? revised enable/ shutdown pin section ....................................................................................................................... 16 ? added input protection section ........................................................................................................................................... 16 ? added figure 39 ................................................................................................................................................................. 17 ? added figure 41 ................................................................................................................................................................. 19 ? changed figure 43 ............................................................................................................................................................. 20 ? changed ideality factor value ............................................................................................................................................. 21 ? changed figure 52 ............................................................................................................................................................. 25 ? corrected signal indicators shown in figure 53 .................................................................................................................. 26 ? updated footnote (1) to figure 54 ...................................................................................................................................... 26 ? changed footnote (2) to figure 54 ..................................................................................................................................... 26 ? changed footnote (2) to figure 55 ..................................................................................................................................... 27 ? updated footnote (3) to figure 55 ...................................................................................................................................... 27 ? revised figure 58 ............................................................................................................................................................... 28 changes from revision c (november, 2009) to revision d page ? deleted references to htssop-20 (pwp) package throughout document; this package version will not be manufactured ........................................................................................................................................................................ 1 ? removed htssop-20 (pwp) package option and footnote (2) from package/ordering information table ....................... 2 ? deleted htssop-20 pwp package thermal resistance information in electrical characteristics table .............................. 5 ? 2008 C 2011, texas instruments incorporated submit documentation feedback 29 product folder link(s): opa564
package option addendum www.ti.com 15-dec-2010 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ ball finish msl peak temp (3) samples (requires login) opa564aidwd active hsop dwd 20 25 green (rohs & no sb/br) cu nipdau level-2-260c-1 year purchase samples opa564aidwdr active hsop dwd 20 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year request free samples OPA564AIDWP active so powerpad dwp 20 25 green (rohs & no sb/br) cu nipdau level-2-260c-1 year purchase samples OPA564AIDWPr active so powerpad dwp 20 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year request free samples (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.

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